Job Description:
" Develop testbenches in UVM, write tests, sequences, agents, functional coverage, assertions and verification plans
" Craft automated verification flows
" Be able to influence and advance our SOC verification methodology.
" Have the opportunity to coach and mentor other members of the team and become a focal point in the group.
" Participate in verification reviews and recommend improvements
Job Qualifications:
" BSC. in Electrical Engineering/ Computer Science
" Experience of 5 years with verification techniques and the full verification life cycle of at least 2 chips
" Experience in developing test benches and verification environments from scratch
" Excellent knowledge and hands on experience of UVM
" Experience with complex designs and advanced debug skills ability
" Excellent presentation and interpersonal skills with a demonstrated ability to communicate complex technical concepts
" Scripting skills in Python/ Perl/ TCL
Company Occupation:
Video/Audio Related, High Tech, Semiconductor/capital equipment
Company Size:
Large (150+)